While reading about Daniel Dib's (CCIE Candidate) 2nd CCIE attempt, I found that he posted a nice MPLS troubleshooting scenario at his blog. It looked challenging, so I loaded the initials on my rack and tried to fix it. There were few reasons I would say behind that.
1. I love to solve technical challenges
2. I wanted to see if the MPLS troubleshooting approach I developed during my CCIE R&S Lab attempt about an year ago is still helpful. Which can be found here:
I must say I'll be taking some time again to add few more things into it since Daniel's MPLS Challenge had few hidden challenges which were not covered into my approach.
Here is the URL to challenge:
Also the original post didn't include details, which I personally like to be documented to make life easier. So my personally updated diagram can be find below:
Total time taken to fix the issues : 9 Mins